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Defender-Adversary Arms Race of Logic Locking

May 25, 2021 10:00~11:40 (KST)

Chip-Hong Chang, Nanyang Technological University, Singapore

Yue Zheng, Nanyang Technological University, Singapore


This tutorial will debunk the belief that the integrated circuit (IC) supply chain is well-protected with high barriers. The illusion that hardware modules are substantially more trustable and easier to protect than its software counterparts due to deterring reverse engineering cost of highly miniaturized dense integration has been invalided once and again by reported backdoors on embedded hardware and untraceable break-ins of networking systems running on fake and subverted chips. The situation is aggravated by the geographical dispersion of chip design activities and the heavy reliance on third-party hardware intellectual properties (IPs). Counterfeit chips pose a major threat to all stakeholders in the IC supply chain, from designers, manufacturers, system integrators to end-users. In view of the severe consequence of potentially degraded quality, reliability and performance that they caused to the electronic equipment and critical infrastructure, a plethora of solutions have been proposed to enhance the security and trust of IC supply chain, collectively referred to as design for trust techniques. These defenses include watermarking that embeds a designer’s signature into the design, metering that tags each copy of the IC and controls the tags throughout the product lifetime, gate camouflaging that introduces indistinguishable structures at the layout-level, split manufacturing that involves partial fabrication at two separate foundries, and logic locking that locks a design with key-controlled protection. Since its inception in 2008, the attacks and defenses of logic locking give a new slant to the defender-adversary arms race in hardware assurance. This tutorial will focus on logic locking and logic obfuscation as an active protection against piracy and counterfeiting, and on certain restricted models of reverse engineering attacks. Thought-provoking questions will also be posted on whether the latest major shortcomings of state-of-the-art logic locking schemes are surmountable.

  • 1. Part I. Introduction to Hardware Trust
    1. 1-1 Design for trust techniques
    2. 1-2 Key gates, insertion and activation methods
    3. 1-3 Combinational logic locking attacks:
      • Sensitization attack
      • Logic cone analysis attack
    4. 1-4 Pre-SAT logic locking defenses
      • Random logic locking (RLL)
      • Fault analysis-based logic locking (FLL)
      • Strong logic locking (SLL)

  • 2. Part II. Post-SAT Combinational and Sequential Circuit Logic Locks
    1. 2-1 Combinational circuit logic locks
      • Boolean Satisfiability (SAT) attack
      • Point function-based logic locks: SAR lock, Anti-SAT
      • Removal attacks: SPS, AGR
      • Strip functionality logic locks (TTL, SFLL)
    2. 2-2 Sequential circuit logic locks
      • Boosted FSM
      • Hardware protection through obfuscation of netlist (HARPOON)
      • Interlocking FSM
      • Performance Locking (DLL)
    3. 2-3 Discussion and conclusion: Is it the end of the story?


Chip-Hong Chang received the B.Eng. (Hons.) degree from the National University of Singapore, in 1989, and the M. Eng. and Ph.D. degrees from Nanyang Technological University (NTU), Singapore, in 1993 and 1998, respectively. He served as a Technical Consultant in industry prior to joining the School of Electrical and Electronic Engineering (EEE), NTU, in 1999, where he is currently an Associate Professor. He holds joint appointments with the university as Assistant Chair of Alumni of the School of EEE from June 2008 to May 2014, Deputy Director of the Center for High Performance Embedded Systems from 2000 to 2011, and Program Director of the Center for Integrated Circuits and Systems from 2003 to 2009. He has coedited 5 books (of which the books entitled ‘Secure System Design and Trustable Computing’ published by Springer and ‘Frontier in Hardware Security and Trust: Theory, Design and Practices’ published by IET are related to this tutorial), 13 book chapters, more than 100 international journal papers (more than 70 are in IEEE Journals) and more than 170 refereed international conference papers. He has been well recognized for his research contributions in hardware security and trustable computing, lowpower and fault-tolerant computing, residue number systems, digital signal and image processing. He graduated more than 20 PhD students, 10 MEng students, more than 20 MSc. students and more than 100 final year undergraduate project students. He has delivered several keynotes and more than 40 invited colloquia, including tutorials at the 2017 Asia and South Pacific Design Automation Conference (ASP-DAC 2017), the 2017 IEEE International Symposium on Circuits and Systems (ISCAS 2017), and the Advance CMOS Technology Winter School (ACTS 2020). He is the recipient of the 2006 NTU Research Outstanding and Award Recognition Scheme, 2007 British High Commission Collaboration Development Award for Microelectronics and Embedded Systems and Canada Microsystems Strategic Alliance of Quebec Collaboration Development Award, co-recipient of the PrimeAsia-2010 Gold Leaf and Silver Leaf Certificates, and coauthor of the finalist of AsianHOST 2017 and AsianHOST 2019 Cisco best paper award, ISCAS 2015 best student paper award competition and VLSI 95 best paper award.

Dr. Chang currently serves as the Senior Area Editor of IEEE Transactions on Information Forensic and Security (TIFS), and Associate Editor of the IEEE Transactions on Circuits and Systems-I (TCAS-I) and IEEE Transactions on Very Large Scale Integration (TVLSI) Systems. He also served in past as the Associate Editor of the IEEE TIFS and IEEE 4 Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) from 2016 to 2019, IEEE Access from 2013 to 2019, IEEE TCAS-I from 2010 to 2013, Integration, the VLSI Journal from 2013 to 2015, Springer Journal of Hardware and System Security from 2016 to 2020 and Microelectronics Journal from 2014 to 2020. He also guest edited eight journal special issues including IEEE TCAS-I, IEEE Transactions on Dependable and Secure Computing (TDSC), IEEE TCAD and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), of which four are related to hardware security. He has served key appointments in the organizing and technical program committees of more than 60 international conferences (mostly IEEE), including the General Co-Chair of 2018 IEEE Asia-Pacific Conference on Circuits and Systems and the inaugural Workshop Chair and Steering Committee of the ACM CCS satellite workshop on Attacks and Solutions in Hardware Security. He is the 2018-2019 IEEE CASS Distinguished Lecturer, a Fellow of the IEEE and the IET. He is also a member of the 2019 and 2020 IEEE CASS Fellow Elevation Committee and 2020 IEEE CASS Distinguished Lecture Program Selection Committee.

Yue Zheng received the B.Eng degree from the School of Communication and Information Engineering, Shanghai University (SHU), China, in 2015; and the Ph.D degree from the School of Electrical and Electronic Engineering (EEE), Nanyang Technological University (NTU), Singapore, in 2020. She was a visiting scholar to Kyoto University from March to June 2019. Currently, she is a research fellow in the School of EEE at NTU, Singapore. Her areas of research include hardware security, physical unclonable function, authentication protocols and so on. She has published 5 IEEE Journal and Magazine papers, including Transactions on Information Forensics and Security (TIFS), Transactions on Industrial Electronics (TIE), Transactions on Emerging Topics in Computing (TETC) and IEEE Circuits and System Magazine, and 7 IEEE Conferences, including International Symposium on Circuits and Systems (ISCAS), Asian Hardware Oriented Security and Trust Symposium (AsianHOST) and International Conference on Consumer Electronics (ICCE). Dr. Zheng was an invited speaker at the 2020 CCF China Test Conference and the 2020 International Young Scholars Forum of Zhejiang University. Her special session proposal entitled “Hardware Security in the New Wave of Digital Technology Revolution” has been accepted by ISCAS 2021. She is an active member of IEEE and CAS society. She has served as a reviewer for ISCAS, AsianHOST, IEEE Transactions on Circuits and Systems-I (TCASI), IEEE Transactions on Very Large Scale Integration Systems (TVLSI) and etc. since 2016.


Fundamentals of Grid-Connected Power Converters in Power Quality Compensation

May 26, 2021 16:00~17:40 (KST)

Chi-Seng Lam, University of Macau, China


With the increase usage of the power electronics devices and motor loadings (such as: power converters, adjustable speed drives, bulk rectifiers, power supplies, elevators, large air conditioning systems, etc.), and also rapid increase in renewable energy generation systems in power grid, the power quality (PQ) problems become more serious, especially for lower power factor, harmonic pollution, unbalanced current, etc., which strongly affects the performance, efficiency and reliability of the power grid. Therefore, implementation of power filters is one of the effective solutions for solving the aforementioned PQ problems. In this presentation, the PQ issues, their impacts and standards to govern different PQ problems will be introduced. To address the PQ problems, the basic principles of active PQ compensators based on the grid-connected power converters will be presented. In addition, the mathematical models, parameter design methods and advanced control strategies for the cost-effective hybrid active power filters in PQ compensation will be discussed in details. Finally, a practical application example and the future trends for the hybrid active power filter development will be introduced.

  • 1. Power Quality, Impacts and Standards
    1. Causes of power quality issues, their impacts and standards
    2. Review of power quality compensators and their market
    3. Grid-connected power converters
    4. Basic principle for active power quality compensation
  • 2. Active Power Filters for Power Quality Compensation
    1. Design and control of hybrid active power filter
    2. Design and control of thyristor controlled hybrid active power filter
  • 3. Practical Application Example and Future Trends
    1. Practical application example of hybrid active power filter
    2. Future trends in hybrid active power filters
      • - Control advances in hybrid active power filters
      • - Hybrid active power filters with photovoltaic power generation
  • 4. Final Wrap-up and Discussions


Chi-Seng Lam (Senior Member, IEEE) received the Ph.D. degree in electrical and electronics engineering from the University of Macau (UM), Macao, China, in 2012. He completed Clare Hall Study Programme at the University of Cambridge, Cambridge, UK in 2019. From 2006 to 2009, he was an Electrical and Mechanical Engineer with UM, responsible for the environmental protection and energy saving projects. From 2009 to 2012, he simultaneously worked as a Laboratory Technician at UM, and pursued his Ph.D. degree in part-time at UM. In 2013, he was a Post-Doctoral Fellow with The Hong Kong Polytechnic University, Hong Kong, China. He is currently an Associate Professor with the State Key Laboratory of Analog and Mixed-Signal VLSI and the Institute of Microelectronics, UM, and also with the Department of Electrical and Computer Engineering, Faculty of Science and Technology, UM. He has co-authored or co-edited four books: Design and Control of Hybrid Active Power Filters (Springer, 2014), Parallel Power Electronics Filters in Three-phase Four-wire Systems - Principle, Control and Design (Springer, 2016), Tutorials in Circuits and Systems Selected Topics in Power, RF, and Mixed-Signal ICs (River Publishers, 2017) and Adaptive Hybrid Active Power Filters (Springer, 2019) and more than 120 technical journals and conference papers (>50 IEEE Transactions & IET journals). He holds four U.S. and two Chinese patents. His research interests include power electronics converters, power quality compensators, renewable energy generation, wireless power transfer, integrated power electronics controllers, power management integrated circuits, and FPGA/DSP based power electronics system. His developed current quality compensation device has been put into practical usage in Macao Water Supply Company Limited in 2014, with a full-load efficiency of up to 98.8%.

Dr. Lam served as a member for the Organizing Committee or Technical Program Committee of IEEE international conferences, including IECON 2020, IECON 2019, ASSCC 2019, APPEEC 2019, IECON 2018, IESES 2018, ASP-DAC 2016 and TENCON 2015. He was a Tutorial Speaker of The 2020 46th Annual Conference of the IEEE Industrial Electronics Society and The 2019 11th IEEE PES Asia-Pacific Power and Energy Engineering Conference. He is also a member of many Technical Committees of the IEEE Circuits and Systems Society and IEEE Industrial Electronics Society. He was the Vice-Chair of the IEEE Macau Section from 2016 to 2020 and the Chair of the IEEE Macau CAS Chapter from 2017 to 2018. He is currently the Chair of the IEEE Macau IES Chapter and the Power Quality Subcommittee Chair of the IEEE IES Technical Committee on Power Electronics. He currently serves as an Associate Editor for IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS and IEEE ACCESS, and a Guest Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS and the IET POWER ELECTRONICS.

Dr. Lam was a recipient or co-recipient of the IEEE PES Chapter Outstanding Engineer Award in 2016, the IEEE Member Recruitment and Recovery Committee Certificate of Recognition for Outstanding Performance in Macau Section in 2019, the Best Track Paper Award of the APPEEC 2019, the Best Paper Award of the ICTA 2019, the Merit Paper Award of the 3rd RIUPEEEC Conference in 2005, the Macao Science and Technology Invention Award (Second Class and Third Class) and the Research and Development Award for Postgraduates (Ph.D.) in 2018, 2014 and 2012, respectively. He also received Macao Government Ph.D. Research Scholarship from 2009 to 2012. His supervised or advised students obtained more than 30 student academic, science and technology and competition awards.


Artificial Intelligence for 5G and Beyond 5G: Implementations, Algorithms, and Optimizations

May 27, 2021 10:00~11:40 (KST)

Chuan Zhang, Southeast University, China


Due to its undoubted significance, research combining “AI” and “5G and B5G” has drawn lots of attentions from both academia and industry. Although some initiatives related to “AI for 5G and B5G” have been named, their design, implementation, and optimization are unfortunately not complete and of course in infancy. Having lots of potential for AI’s new innovations, advances are required in network architectures, signal processing solutions, semiconductor technologies as well as in its optimization regarding the overall wireless system design. Much of the research has scattered on the design, implementation, and optimization of the corresponding circuits and systems.

This tutorial would like to emphasize its uniqueness on “AI for 5G and B5G” related VLSI/IC designs and help readers to know the cutting-edge progresses from the perspective of circuits and systems. With a focus on bridging the gaps between theory and practical implementations, the goal of this tutorial is to demonstrate the latest research progress on circuits and systems design for efficiently realizing machine learning in wireless communications. The tutorial will bring together academic and industrial aspects to identify technical challenges and recent results related to this area, including Big Data Processing, Artificial Intelligence, Internet of Things, and 5G and Multi-Gigabit Optoelectronics Comm.

  • 1. Introduction of Electromagnetic-Acoustic Sensing and Imaging Circuits and Systems
    1. 1-1 Introduction to massive MIMO system model
    2. 1-2 Using AI for Nnar-MMSE detectors of massive MIMO
    3. 1-3 Using AI for near-optimal detectors of massive MIMO
    4. 1-4 Hybrid precoding platforms for 5G mmWave
    1. 2-1 Circuits and systems for AI-aided non-orthogonal modulations
    2. 2-2 Circuits and systems for AI-aided FMBC equalizations
    3. 2-3 Circuits and systems for AI-aided new waveform related designs
    1. 3-1 Circuits and systems for LDPC codes
    2. 3-2 Circuits and systems for AI-aided SC/SCL polar decoders
    3. 3-3 Circuits and systems for AI-aided BP polar decoders
    4. 3-4 Hardware-software co-design based flexible channel decoders
    1. 4-1. Achievements and challenges
    2. 4-2. Future research directions


Chuan Zhang received the B.E. degree (summa cum laude) in microelectronics and the M.E. degree (top-1 student) in very-large scale integration (VLSI) design from Nanjing University, Nanjing, China, in 2006 and 2009, respectively, and the M.S.E.E. and Ph.D. degrees from the Department of Electrical and Computer Engineering, University of Minnesota, Twin Cities (UMN), USA, in 2012. He is currently the Excellence Professor and the Purple Mountain Professor with Southeast University. He is also with the LEADS, National Mobile Communications Research Laboratory, Quantum Information Center of Southeast University, and the Purple Mountain Laboratories, Nanjing, China. His current research interests include lowpower high-speed VLSI design for digital signal processing and digital communication, bio-chemical computation and neuromorphic engineering, and quantum communication. Dr. Zhang serves as an Associate Editor for the IEEE TRANSACTIONS ON SIGNAL PROCESSING and IEEE OPEN JOURNAL OF CIRCUITS AND SYSTEMS. He serves as a Corresponding Guest Editor for the IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS twice. He is also the Secretary of the Circuits and Systems for Communications TC of the IEEE Circuits and Systems Society. He is also a member of the Seasonal School of Signal Processing and Design and Implementation of Signal Processing Systems TC of the IEEE Signal Processing Society, and Circuits and Systems for Communications TC, VLSI Systems and Applications TC, and Digital Signal Processing TC of the IEEE Circuits and Systems Society. He received the Best Contribution Award of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) in 2018, the Best Paper Award in 2016, the Best (Student) Paper Award of the IEEE International Conference on DSP in 2016, three Best (Student) Paper Awards of the IEEE International Conference on ASIC in 2015, 2017, and 2019, the Best Paper Award Nomination of the IEEE Workshop on Signal Processing Systems in 2015, three Excellent Paper Awards and two Excellent Poster Presentation Awards of the International Collaboration Symposium on Information Production and Systems from 2016 to 2018, the Outstanding Achievement Award of the Intel Collaborative Research Institute in 2018, and the Merit (Student) Paper Award of the IEEE APCCAS in 2008. He also received the Three-Year University-Wide Graduate School Fellowship of UMN and the Doctoral Dissertation Fellowship of UMN.

Synopsys Mini Tutorials


Unleashing PrimeSim Continuum

May 26, 2021 10:00~10:30

Hany Elhak, Synopsys


Today’s hyper-convergent systems consist of larger and faster memories, analog front-end devices and 100GB+ interconnects. Signoff time of these complex designs scale as advanced process nodes present increased parasitics, process variability and reduced margins.  PrimeSim Continuum addresses the systemic complexity of such hyper-convergent systems with a unified workflow of signoff quality simulation engines tuned for analog, mixed-signal, RF, custom digital and memory designs. PrimeSim Continuum uses next-generation GPU-accelerated SPICE and FastSPICE architectures to improve time-to-results and cost of results.


Hany Elhak is the Group Director of Product Management and Marketing of the circuit simulation and design environment product lines at Synopsys. He has more than 20 years of EDA experience spanning both technical and marketing responsibilities. Prior to EDA, Hany worked as RF designer, designing RF ICs for cellular and wireless networking standards. Hany holds B.Sc. and M.Sc. degrees in Electrical Engineering from Ain Shams University, Cairo and MBA from UC Berkeley, Haas School of Business.


PrimeWave: The Next Generation Design Environment

May 26, 2021 10:30~11:00

Samad Parekh, Synopsys


Modern Circuit designs require new ways of analysis and characterization. The PrimeWave Design Environment offers a single platform for analog, mixed-signal and RF analysis with integration of the PrimeSim Continuum, powerful waveform viewing and post-processing functions, and flexible scripting capability.


Samad Parekh is the Product Manager for Spice Simulation and Design Environment products at Synopsys. He has 10 years of experience serving as a senior member of the Synopsys Applications Engineering team supporting Analog and Custom tools. Prior to Synopsys, Samad worked as an RF designer for 6 years designing RF and microwave circuits for the cellular and aerospace markets. Samad holds a BSEE from UCLA and MSEE from UC Irvine.